بناء محاكي لبنيتي المعالجات فائقة التدرج والمعالجات الشعاعية ومقارنة أدائهما في معالجة التفرع على مستوى البيانات
Abstract
تم في هذه الورقة عرض لبنى المعالجات المتوازية والتركيز على بنيتين أساسيتين من هذه البنى وهي بنية المعالج فائق التدرج (Superscalar Processor) وبنية المعالج الشعاعي (Vector Processor)، وبالإعتماد على الخصائص الأساسية لكل منها تم بناء محاكي لهذه البنى يحاكي آلية عملها برمجياً بهدف المقارنة بين أدائها فيما يخص التوازي على مستوى البيانات (Data Level Parallelism DLP) والتوازي على مستوى التعليمات (Instruction Level Parallelism ILP).
تبين النتائج أن فعالية تنفيذ التعليمات على التوازي تعتمد بشكل كبير وأساسي على اختيار بنية المعالج المناسبة للتنفيذ وفق نوع التوازي الممكن تطبيقه على التعليمات، وأن ميزات الشعاع في البنية الشعاعية تحقق تحسين ملحوظ في الأداء لايمكن إغفاله في تنفيذ عمليات DLP وتبسيط للكود البرمجي وتقليل لعدد التعليمات، ويشكل المحاكي المقدم نواة جيدة يمكن تطويرها والإضافة عليها خاصة فيما يخص المجال التعليمي لطلاب علوم وهندسة الحاسب والمجال البحثي.
This paper presents parallel computers architectures especially Superscalar processors and Vector processors, building a simulator depending on the basic characteristics for each architecture, the simulator simulates their mechanism of work programmatically at the aim of comparing the performance of the two architectures in executing Data Level Parallelism (DLP) and Instruction Level Parallelism ILP.
The results shows that the effectiveness of executing instructions in parallel depends significantly on choosing the appropriate architecture for execution, according to the type of parallelism that can be applied to instructions, and the vector features in the vector architecture achieve remarkable improvement in performance that cannot be ignored in execution of DLP, simplify the code and reduce the number of instruction. The provided simulator is a good core that can be developed and modified especially in the field of education for the students of Computer Science and Engineering and the research field.
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