دراسة إمكانية تخفيض الاستطاعة المستهلكة في دارات CMOS بإنقاص فعالية التبديل

Authors

  • أحلام محمود

Abstract

يهدف البحث إلى دراسة تخفيض الاستطاعة المستهلكة في الدارات الرقمية نوع CMOS وإلى تطوير طرق جديدة في هذا المجال والحصول على نتائج عملية جديدة قابلة للتطبيق في مجال تطوير الأجهزة الإلكترونية المتكاملة عالية الاندماج VLSI ، تم في هذا البحث دراسة تخفيض الاستطاعة المستهلكة الديناميكية بتخفيض فعالية التبديل حيث تم تغيير البنية الهندسية للدارة الرقمية على الاستطاعة المستهلكة ، واستخدمت تراكيب مختلفة للدارة.

حيث تم الحصول على نتائج جيدة بطريقة المحاكاة باستخدام برنامج ال Matlab حيث تم تخفيض قدره 10 %مما يساعد في تحقيق مواصفات عالية في تصميم الدارات.

This research aims to reduce the possible consumption in CMOS digital circuit type and to develop new methods in this area and get the results of a new process applicable in the field of the development of integrated electronic devices of high integration VLSI, has been in this study the possible reduction of consumer dynamic by Reduction Of switching Activit where the researcher changed the architecture of digital circuit on the possible consuming, and she used different combinations of the circuit.

the researcher got good results in a manner using the Matlab simulation program where she got reduction of 10%, which helps us to achieve high standards in the design of integrated circuits.

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Published

2018-11-06

How to Cite

1.
محمود أ. دراسة إمكانية تخفيض الاستطاعة المستهلكة في دارات CMOS بإنقاص فعالية التبديل. Tuj-eng [Internet]. 2018Nov.6 [cited 2025Jul.12];40(3). Available from: http://www.journal.tishreen.edu.sy/index.php/engscnc/article/view/4508

Issue

Vol. 40 No. 3 (2018): العلوم الهندسية

Section

Articles

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